Likely shipping w/o the proper documentation to enable nextpnr and similar tools, as it's tradition in altera.
I will always choose the vendors that do things properly, when they're even an option.
I will always choose the vendors that do things properly, when they're even an option.
Next best thing? The mature reverse-engineered families nextpnr[0] supports.
0. https://github.com/YosysHQ/nextpnrhttps://github.com/YosysHQ...
And that's not a great option, frankly. GateMate is a strange design with major performance issues, like the lack of a dedicated clock network.
We're starting to see open source FPGAs but they are miniscule: https://tinytapeout.com/chips/ttihp26a/tt_um_fabulous_ihp_26...
The reality is just that it's a lot of work, and Agilex is probably an order of magnitude (or two orders) more complex in scope than any existing FPGA with reversed or open specs. It's going to require a lot of expertise even with superhuman assistance. Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience. If people are going to Claude shit out in the EDA space I'd frankly rather have them work on more important day to day mundane things that are still lacking but important, eg improved performance, power analysis/floorplanning, sdc/constraint based clock synthesis and related tools, etc.
And yes, breaking your device is also a risk for some features too (eg Lattice ECP5 bitstream encryption has never been RE'd since it requires blowing fuses.) But the actual problem requires far more expertise than having Claude reverse engineer gameboy games.
The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.