As you say, the main reason for using a wafer with a double area is to double the number of transistors that can be made on a wafer, reducing their fabrication cost.

Nonetheless, the reduction in fabrication cost is greater for large-area devices, for 2 reasons.

One is that on bigger wafers less area is wasted at the periphery, where in many places a full die does not fit inside the circle, so an area corresponding with a fraction of a die remains unused. The amount of such wasted area grows quickly with the size of the die.

The second reason is that the dies that are close to the wafer edge, even if they fit inside they have worse yields than the dies that are far from the edge. Again, the proportion of such dies with worse yields increases with the die size and it is lower for bigger wafers.