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I was looking for the lowest claim in this thread, as I managed to get a nano LLM running in the ≈3mb of SRAM of an FPGA with zero DDR in the loop at 20k tok/s, but 2mb on a 80386, great job.

Have you got a write up for it?

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I ran YOLO on an FPGA for my bachlor's project degree project like 7 years ago, but this is even more interesting, and I think we can push bigger models with weight streaming. I still have an FPGA lying around.

I haven't written a new blog post for it yet but there's currently a demo live of my FPGA running bonsai 8b on the same FPGA here

https://www.mikeayles.com/blog/on-chip-llm-kv260/

Its right up against the wall of DDR bandwidth, so I'm trying every trick in the book to get the speed up

Decent!! Also I love the idea of the live chat, would you mind if I put a reference to it on my repo?

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