You're implying it could be done if whatever load distribution and power condition that's done outside of the chip, which consists of a lot of analog components to help manage rapid changes in power consumption, could be somehow packaged inside the chip.

So, in rough terms, the internals of a large-scale chip are not one big integrated circuit, but a large number of smaller modules that are massively interconnected, then?

That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? It's just usually the case that more power-hungry chips have more pins, as the 2011 socket is for Intel's flagship CPUs, the 1155 ones more commodity-oriented.

With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? I'm not sure what the presumption is in real-world CPU design.