This is certainly an interesting read, and stack machines have a long history among alternative CPU architectures. But I think that the complaints this (admittedly 18-year-old) article levels against mainstream CPUs are largely unfounded with today's chips. Or at least, increasing complexity is not a cause of decreasing performance, as is claimed, but rather a major reason that we've had such amazing leaps in computing power. Pipelining, branch prediction, out-of-order execution, multilevel caching, and clever tricks in many places all enable 3GHz CPUs that can peak at 4 instructions per cycle today. You'll lose two orders of magnitude in performance if you try to throw all that out and go back to basics, as the article suggests. (You may reduce more than two orders of magnitude in power, and power is an interesting constraint in today's systems; but the article didn't specify low power as the goal.)

- "Modern RISCs are slow because instructions take many cycles to execute": Latency is irrelevant as long as the pipeline remains filled. Pipeline length only matters when it's in the critical path, e.g. cycles from fetch to branch execution determines the bubble size on a mispredicted branch.

- "The pipeline must be flushed and refilled on branches"? Only on mispredicts, which are rare with good predictors on most code.

- "Cache makes the system more complex and expensive"? But it also is the only way to have acceptable performance when DRAM accesses take 200 cycles or more.

- "RISCs are slow at calls and returns" due to many registers? A good compiler will only save as many registers as it clobbers; more registers reduce register pressure and spills/fills, improving perf. (This is a net perf increase from x86-32 to x86-64, for example.) The only significant cost is additional context-switch overhead.