To your point about "uninitialized variable" nets, if the net was truly a singleton it would show up as such in a netlist report. This capability existed in board design tools I used 30 years ago. What might have happened is a renamed net might have been split into two different nets. E.g. a net that connected 10 places became two nets, one to 8 places, another to 2 places. Not a singleton.
There are additional checks that netlist generation tools can do. E.g. does every net have a "driver" or "output" on it, or does it consist of all "inputs". Absence of driver can easily be flagged as an error. However, there is one wrinkle. Sometimes, nets are "busses" and are bidirectional. Each pin of the net can be either an input or an output at various times. That's harder to detect as an error.
There are many ways to avoid problems like this. Two common ones: 1) READ THE LOGS. I'd bet even money that your problem shows up in the logs as a singleton net or as a net without a driver. 2) SIMULATE. Board functional simulation has been possible for over 30 years; it's not always done. Did your engineer simulate his design? Why didn't his simulation catch the problem?
Sometimes, in board design (as in FPGA design) it's faster and certainly easier to just get 99% of the way there ahead of time and debug the final few errors on the board itself. That might be the case here, so if your company made this decision a priori, then you shouldn't be surprised if you need to spend some time debugging a few simple errors.
BTW that sort of sloppiness just wouldn't fly in chip design. Chips are usually far far far too complicated; extensive pre-tapeout simulation is de rigueur. And it takes weeks (if you have much money and a very good relationship with a fab) or months to get revised silicon. Much easier to do a few cuts and jumpers to a board than to do a silicon spin.
As to "refactoring support", most CAD systems I was familiar with didn't have an easy way to rename a net across multiple "pages" of a board design. Maybe the tools have gotten better. IMO that sort of refactoring (if done extensively) is a losing proposition anyway. You're much better off with careful attention to detail up front. You should be very careful renaming nets that cross schematic pages; you wouldn't have the problem if you carefully thought about the names before you created the schematic.
In summary, even the best tools won't help a sloppy designer.