You are correct in the edge sensitive set/reset from a simulation standpoint. If reset is asserted, then set is asserted, then reset is de-asserted, then the flip-flop will remain in reset. It's not truly asynchronous from a simulation standpoint.

This could be fixed by using:

always @(posedge clk or rst or set)

I am guessing the thing that throws a verilog designer off the trail is that "always @(posedge clk or negedge rst)" is commonly used for asynchronous reset in ASICs (if you are using it in FPGA's except for the DCM's and as input to a clk-rst module.... stop), and this works just fine but if you want to do a d flip flop with an asynchronous SR condition, you can't use "negedge" on the rst signal.

However, synthesis will probably treat it asynchronously. Of course this is also bad because there will be a simulation/synthesis mismatch.

At any rate, the question is a bit ambiguous due to the unclear vhdl code.