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I'm reminded of Viva from Starbridge which was supposed to make FPGA "programs" easier to build and debug - using large generic blocks.

I have no idea what happened to them, but I suppose the problem was harder than they believed or at least claimed.

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It got bought by Data I/O and renamed Azido. I've used it briefly and it made me beg to go back to Verilog.

Wow. That really says something (to me anyway), begging to go back to Verilog.

There are a lot of pain points in the HDLs, but it seems like Verilog has more than the others.

I saw someone working on a clojure HDL, I think it might have compiled down to or emitted Verilog. I thought it was more confusing than the HDLs to begin with, but depending on one's background it might make more sense.

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