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One of the most irritating ones I found was in an FPGA. There was a bug in the FPGA code with an initial state which would only fail to initiate an ADC converter correctly if the temperature was somewhere around 75F.

So at room (lab) temperature, it was fine. Out in the "field", which was 1000 feet away from the lab, nothing would work.

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Did you run a post-PAR (timing) simulation on that? On designs with low timing slack or large area occupation this is really important, otherwise you may easily violate setup/hold time constraints in what are usually very nondeterministic ways. This is, in fact, one of the reasons why ASIC development is ~80% verification.

We had a bug of the kind once, where a Microblaze core would fail to boot the Linux image after what seemed a trivial modification in the peripheral code, but it turns out we were packing the logic so tightly that this change blew the timing on some critical net. Ah, the joys of digital design.

I just want to point out that nowadays people don't usually catch timing issues in digital designs with simulation. It's mostly done by static timing analysis tools such as PrimeTime, which is much more accurate, efficient, and thorough than running logic simulations with annotated delays.

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