New Chinese Supercomputer Goes Beta

The article was a bit light on the interconnect information: It's called the TH Express-2 (proprietary) and from this report[1]:

> The TH Express-2 uses a fat tree topology with 13 switches each of 576 ports at the top level. This is an optoelectronics hybrid transport technology. Running a proprietary network. The interconnect uses their own chip set. The high radix router ASIC called NRC has a 90 nm feature size with a 17.16x17.16 mm die and 2577 pins. The throughput of a single NRC is 2.56 Tbps. The network interface ASIC called NIC has the same feature size and package as the NIC, the die size is 10.76x10.76 mm, 675 pins and uses PCI-E G2 16X. A broadcast operation via MPI was running at 6.36 GB/s and the latency measured with 1K of data within 12,000 nodes is about 9 us.

[1]: http://www.netlib.org/utk/people/JackDongarra/PAPERS/tianhe-...

One really cool part of this supercomputer that is left out of this article is that it uses the Intel Larabee/Phi co-processor, at least 48000 of them.

http://en.wikipedia.org/wiki/Larrabee_(microarchitecture)

Other Chinese computers were plagued by reliability issues and poor IO performance, mainly due to unwarranted focus on LINPACK performance. We shall see if they fixed these problems.

Interesting that the Chinese have adopted x86 for their supercomputers; I remember a few years ago they were experimenting with MIPS and there was a huge effort to make it the "national ISA" - and lots of tablet and media player SoCs came out with MIPS cores (still many today, but they seem to be gradually shifting into ARM instead.)

Tianhe 2 has some Chinese SPARC cores in it too but it looks like they're just being used for control/management functions.