Comment by zw123456 | Hacker News Reader

Comment by zw123456 | Hacker News Reader

The drive to smaller gate structures is because a MOSFET transistor gate is essentially a capacitor, and as such, it takes time to charge and discharge the capacitance of the gate. So to further increase the performance, one must reduce the capacitance of the gate. The gate is basically and RC circuit. The easiest way to reduce the capacitance is to reduce the physical size of the gate. The size of the gate is directly proportional to the capacitance. Once you get down to a few atoms wide, which they are approaching now, then quantum effects kick in and it starts getting impractical to go further. The alternatives for the next generation have to do with attacking the R part of the equation which is what they mean when they talk about electron mobility. Other approaches that are unrelated to the traditional MOSFET are being researched, but there is such a huge amount of IP based on MOSFET any move away from that will incur huge cost in porting over. (think of it as the hardware version of switching to a new programming language). I am not sure what the next gen answer will be as it seemed the author did not either (which tells me he knows what he is talking about).

Wow, you are so wrong, and yet no one has corrected you!

We want to increase gate capacitance, not decrease it. The higher the capacitance, the faster you can invert the channel, and therefore turn the transistor on.

Think of a transistor as a water tap (valve based). Gate capacitance is the sensitivity of the valve to the handle. In this analogy, higher capacitance is equivalent to less effort to turn the handle (to move the valve out of the way and let the water flow).

That's the reason we want to increase the area of the gate (the idea behind FinFET, and all-around gate), and increase its dielectric constant (the idea behind high-k materials).

You're also confused about RC model - perhaps you heard it in the context of a logic gate (as in NAND), and you try to apply it when talking about a transistor gate (as in FinFET). Nope.

I've heard that the whole quantum tunneling stuff is in practical terms bullshit. While it's a real effect (and physicists looove to talk about it), it's virtually irrelevant b/c the overwhelming issues is parasitic capacitances. When you have a 3Ghz clocks, everything acts like a capacitor and you have current leaking all over the place (the smaller the circuit the closer all the elements are).

So transistors in modern processors don't end up switching consistently. There is all sorts of error correction to compensate for that, but it only goes so far.

On the other hand, I heard just this week at imec that currently 30% of the leakage is due to quantum tunneling. Nothing to sneeze at.

The gate leakage current was a serious concern until the High-K gate dielectric was found. It increased the gate dielectric thickness so tunneling current is reduced significantly (exponentially). Nowadays the main problems are subthreshold leakage and dynamic power. Here's a good article about it:

http://spectrum.ieee.org/semiconductors/design/the-highk-sol...

> the main problems are subthreshold leakage and dynamic power.

This is exactly correct. Even at 28nm, many SoCs are intentionally using less than the max manufacturable transistor density, due to dynamic power/thermal constraints.

SRAM is scaling poorly too. It makes up 50-60% of many SoC designs yet at 1500MHz+ its density (Mb/mm^2) looks likely to increase just 1.1X between 28nm and 16nm.

Desktop CPUs are not going to get 32MB on-die caches any time soon. At least not without eDRAM.

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