[by the way, the PDF at http://riscv.org/download.html#tab_isaspec is clear reading]
[by the way, the PDF at http://riscv.org/download.html#tab_isaspec is clear reading]
I am wondering, what the advantage of a zero register is? I thought about supporting direct operations, but adding zero does not make to much sense, same with minus, multiply, division .... OR/AND/XOR does also make not much sense. Storing data into this register also does not make to much sense ... or as garbage tray??? ;) (the hardware implemented garbage tray was once the April fool joke in an IT magazine).
For example, the original MIPS instruction set has these pseudoinstructions:
- li $d, imm (load immediate) is replaced with ori $d, $0, imm (or immediate with the zero register)
- not $d, $s (bitwise complement) is replaced with nor $d, $0, $s (bitwise NOR with the zero register)
... and some others as well.
It's useful for several things. One is as a no-op instruction; as you point out, AND, OR, XOR, etc. with zero are no-ops, and no-ops are sometimes useful for achieving certain alignment in code, or leaving space for instructions to be patched out with other code (which is common for debugging, tracing, and hot-patching of code).
It can also be used for copying from one register to another, without another instruction. "ADD rd, rs1, 0" is a way to write "MOVE rd, rs", so you don't need to waste an extra instruction on that.
0 is also one of the most common values that you want to compare against (many loops can be turned into decrementing a value until it becomes zero, or you're just walking along a data structure or string until you encounter a null value), and so their branch instructions work by comparing two registers and branching to a particular offset. Having a dedicated 0 register means you can always do a compare against 0 and branch in a single instruction, without having to have separate instructions for comparisons against immediates versus comparison of two registers.
[1]: http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-63...
The other examples are also valid, but rather special to RISC architectures ... but of course it does the trick.