What I learned building a parallel processor from scratch
parallella.org
parallella.org
[1] https://twitter.com/justincormack/status/561128891348422657
With only $6M raised, this whole venture is probably a 100 to 1 moonshot to be honest with you.(although as an entrepreneur clearly I have to believe the odds are better than that...). Calxeda raised $100M and went bust, Tilera raised $150M and was sold for $50M, Tabular raised $200M and went bust, the Cell processor supposedly cost $1B to develop, etc.
If you are interested, here is a long list of parallel processor efforts. All of them failed to reached general purpose status:
http://www.adapteva.com/white-papers/the-siren-song-of-paral...
ps: Also, I don't think there was mention of your previous work on the Kickstarter page or boards, was it on purpose (NDA,...) ? Past projects like these really give trust to future clients.
http://www.parallella.org/2015/02/22/what-i-learned-building...
slides [pdf]
http://www.parallella.org/wp-content/uploads/2015/02/chalmer...
cached [html]
https://webcache.googleusercontent.com/search?q=cache:https%...
Yet. People will want good voice recognition. Even if you cannot get that in your phone, your provider will want an energy-efficient solution for running voice recognition for millions of users simultaneously.
Further ahead is the babelfish.
Your phone also may want to use its cameras to figure out who is talking, and adjust its noise suppression depending on the location of the speaker.
Finally, car manufacturers will want small, low-power, cheap stuff to build their self-driving cars.
Hardware like this may strike the right balance between flexibility and power use for problems such as these.
And yes, this may be too weird for most to take the risk of using it, but it may take only one succesvol company to make the jump.
(Otherwise I generally agree with slides: software and features are much more important than performance).
One thing which is rational and helps FPGAs is time to market (vs. a giant SoC with long verification time). If you can get your design to market sooner than anyone else you get to charge a premium which could pay for the extra per-chip cost of FPGAs vs. ASICs.
It would be interesting to have a tile-based chip like this, but with an FPGA-style I/O ring (I mean support many common interfaces including serdes-based but also allow the interchip links). Perhaps you end up with a new form of FPGA.
28nm is pretty cutting edge (many, many steps) and has a number of customers (competing for manufacturing line time).
It's a bummer, but it's a long process. Not to mention, each new chip you spin is $$$, so it's not like you would iteratively fab many prototypes, even if you had a fast turnaround time.
OTOH, if you can't get the fab time below 11 months maybe you should spend more like 24 months on the design.