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Comment by ubercore | Hacker News Reader

The most interesting thing I took from the Mill videos I watched is the way they define the processor features in code. They can describe the whole specification in code, compile and test the CPU. Then get enough information from the simulation to actually put together the layout for the physical cpu. You can add or remove features from the CPU by implementing the proper functions, and test the specification before committing to silicon. My background is software, so maybe it's not as impressive as it sounds, but it really caught my ear as an elegant solution to customizing a processor architecture for different needs.

http://millcomputing.com/docs/specification/

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This is how Gary Tarolli designed first 3DFX chip.

https://www.youtube.com/watch?v=3MghYhf-GhU

What do you mean by code? Most digital chip design is done in Verilog or VHDL which are hardware description languages.

C++ (possibly abusing the preprocessor to abuse the templating system...)

Oh, I learned today that VHDL has (had?) a standardization group called VASG, which is quite a nested acronym:

VASG → VHDL Analysis and Standardization Group → VHSIC Hardware Description Language Analysis and Standardization Group → Very High Speed Integrated Circuit Hardware Description Language Analysis and Standardization Group

Also, some instructions of modern CPUs are implemented in software that resides on the CPU.

http://en.wikipedia.org/wiki/Microcode

Microcode is old.. So 'modern CPUs' --> 'some CPUs'.

Yes but you can also build functional or cycle accurate simulator in software which can give you some information on how the processor could potentially perform. Of course having a soft-core running on an FPGA will most likely give you a more accurate idea of how the processor actually works.

Take a look at Chisel (http://chisel.eecs.berkeley.edu)... they call it a "Hardware Construction Language" instead of a HDL, as you describe how the hardware works in chisel code, which is just a Scala embedded language. It is then able to generate FPGA or VLSI optimized verilog, and a C++ cycle accurate simulator. I have been using it for the past ~9 months designing a new chip.

What is your experience with Chisel? How much more productive are you compared to writing Verilog?

I am interested in trying out new tools, but information on Chisel is pretty sparse.

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