Bitfusion: Supercomputing for the masses
bitfusion.io
bitfusion.io
Thanks for your question, you can take a look at our TCD presentation for an overview: http://techcrunch.com/2015/05/05/bitfusion-helps-developers-...
Bitfusion is a software layer that discovers available hardware accelerators and then automatically applies accelerator libraries, smart load scheduling, and dozens of software optimization techniques to make acceleration “plug and play”.
Specifically, our software is built on top of OpenCL which allows our software to take advantage of any device that supports OCL. It’s a solid basis for hardware compatibility, and it allows us to take advantage of FPGAs that just recently started supporting OCL robustly. Second, we’ve build a bunch of functionality to make simultaneous use of multiple accelerators — even from different vendors and types. This is an important step because a fundamental problem for widespread adoption of heterogeneous hardware is being vendor and device neutral to keep software development sane and tractable. Thirdly, we’ve been developing, curating, and partnering to combine the most promising automatic software optimization tech to deliver to our customers to address app performance more generally.
Hardware acceleration to the masses is *primarily about friction: apis, code optimization, vendor-specific code. Bitfusion is all about bringing this friction down to zero. We love talking about this stuff all day, so send us a note if you'd like to talk more.
Mazhar
Automated X86 to GPU native translation is looking more and more feasible, with some caveats. Especially SIMD operations are a natural fit. But the issues... GPUs are sequentially very slow. Single thread execution is over an order of magnitude slower than for CPUs. Latency between host CPU and GPU is usually significant, measured even in milliseconds. Other than memory bandwidth, CPUs are catching up on GPUs anyways. If x86 SIMD keeps getting wider, we might be just a few years away from CPU and GPU processing power parity.
But FPGAs... Does it place and route itself, or use something like OpenCL as a backend? Or does it make "netlists" out of x86 code and somehow make existing FPGA tools to compile them to chip fabric?
Anyways, when it comes to this product and FPGAs, I believe only when I see!
For FPGAs, OpenCL support is still very new. Both Altera (now Intel) and Xilinx have toolchains that compile OpenCL source into gates through first highlevel synthesis and then taking the output through the normal synthesis, implementation, bitstream flow. It's a huge development that should increase adoption of FPGAs for more common use which is why we're excited about it.
Mazhar Bitfusion.io