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Comment by minthd | Hacker News Reader

>> Having this physical reference would really cut the learning curve in computer architecture.

I don't know, i think having a language that supports mixing high and low levels of description to describe a processor and the tools to simulate and play with it could offer much faster learning, since you could focus on learning.

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Indeed, building a VHDL/Verilog CPU is a staple of top-tier EE/CE programs. The rest is just wiring.

Verilog and VHDL are substantial learning curves in themselves. We could really do with a newbie-friendly alternative; I don't know whether http://www.myhdl.org/ might be it.

MYHDL isn't compile-able(synthesizable) to hardware.

I know they teach Chisel, a higher level language , in berkley. Maybe it fits software engineers and would be fun to design cpu's with.

Bah, in that case it shouldn't be calling itself an HDL! Chisel looks more appropriate.

To be fair, it's Hardware Description Language, not Hardware Synthesis Language. HDLs are mostly tools to support V&V, it's just that synthesis is the most convenient way to ensure that an implementation is consistent with the HDL description.

Yeah, I believe originally all the HDLs were intended for simulation of designs which were then implemented by hand. Neither Verilog nor VHDL was processor designed for synthesis, which is probably why it's so quirky.

I checked again , and there's a subset of MyHDL which does support synthesis, but it's at such a low level it's not very different from VHDL/Verilog.

The whole MyHDL is mostly used for verification though.

Please. Of course it is, and that is made very clear on the home page. http://www.myhdl.org/

Verilog and VHDL already simplify hardware design a lot. They seem to have a great learning curve due to the nature of hardware design.

Most people gain a lot of confidence in software development and try to design hardware like they would program a system. And then they complain that Verilog and VHDL is too complex.

Verilog in particular leads you into that trap, though. Because you can write conventional sequential-execution programs in it, and usually have to when writing testbenches. The nomenclature of "process" and "task" imply they behave like software - and they do, in the simulator. Then there are the hoops you sometimes have to jump through in order to get the synthesis to behave as you want: "reg" is not always a D-type flip flop, and is mandatory in some places where it doesn't synthesise to one.

The challenge of Verilog & VHDL is not learning the language, it's learning the paradigm of hardware & HDL. Everything is parallel, nothing is sequential unless otherwise specified.

In themselves they are very simple, basic languages.

It's kind of a pity Notch abandoned 0x10c.

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