To be fair, it's Hardware Description Language, not Hardware Synthesis Language. HDLs are mostly tools to support V&V, it's just that synthesis is the most convenient way to ensure that an implementation is consistent with the HDL description.
Yeah, I believe originally all the HDLs were intended for simulation of designs which were then implemented by hand. Neither Verilog nor VHDL was processor designed for synthesis, which is probably why it's so quirky.
I checked again , and there's a subset of MyHDL which does support synthesis, but it's at such a low level it's not very different from VHDL/Verilog.
The whole MyHDL is mostly used for verification though.