FredFS456

I'm guessing he's downloading "Linux ISOs".

awscli tools can generally do so.

> Place and route has to solve an NP-Complete optimization to figure out where, on the physical die, all the transistors are going to go, given a set of constraints (transistors need to be close enough to their neighbors to achieve the performance requirements).

I've always wondered at the efficiency of the Place and Route step of chip design - I've dabbled in PCB design at the hobbyist level, and any autorouter that I've come across has been complete garbage compared to a person manually solving the puzzle of placing parts and routing a PCB. Is this any different at the SoC level? Are the SoC-level autorouters structured differently? How automated is this step really?