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_chris_on An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]

Spoiler-alert, even your x86 desktop cores struggle to hit more than 1 IPC on most workloads. That's just the reality of cache misses, instruction dependencies, branch prediction, and more.

_chris_on The Ampere Altra Review: 2x 80 Cores Arm Server Performance Monster

The paper you linked to is about embedded controller micro-benchmarks being worse by 5-10%; RISC-V's compressed ISA made some tough decisions to improve density on general-purpose code, not just micro-focused on MCUs. On something larger like SPEC, RISC-V is denser than ARM and x86.

_chris_on Oracle Moving HQ to Austin

There's a reason we wear shoes indoors in Texas...

_chris_on How Microsoft crushed Slack

Slack is a lot better than Teams IMO, but it's hard to justify putting company stuff (like documentation and wikis) into a proprietary platform that could raise prices or disappear at any moment.

With Teams, if you're already under the MS umbrella, it's an easy sell.

_chris_on What do RISC and CISC mean in 2020?

Register moves aren't free, even if you do renaming tricks. They take up fetch bytes, they take up decode slots, they take up a lot more resources than just Regfile/ALU bandwidth.

_chris_on What do RISC and CISC mean in 2020?

> The variable length instructions of x86 mean you can fit more of them in an L1i of a given size.

Unfortunately no, x86 is worse than RISC ISAs like ARMv8 and RISC-V in instruction density.

_chris_on What do RISC and CISC mean in 2020?

>The 16 or 32 architectural registers of the ISA are pretty much irrelevant compared to the capabilities of the out-of-order engine on modern chips.

This can have a big effect on memory traffic due to unnecessary moves and stack pops/pushes.

_chris_on An ex-ARM engineer critiques RISC-V

The problem is that providing extra bits for "sign-extension mode" and "read 32b or 64b" blows through the opcode space very quickly.

_chris_on The TRIPS project: an explicit data graph execution (EDGE) processor

Microsoft and I believe Qualcomm research took this and did two follow-on versions. They gave a joint keynote talk at ISCA (2018?) on their experiences, but I can't seem to find any slides or video on it.

I recall them saying it looked to give them roughly the same performance as state-of-the-art processors with ~30% less power; but that's a hard gamble for the $100Ms required to get to a product (especially if it requires a new ISA).

_chris_on The AMD Radeon Graphics Driver Makes Up Roughly 10.5% of the Linux Kernel

Are they also open-sourcing the tool that generates the committed code? If not, then there's little difference between "generated" and "actual" source code.

_chris_on ULX3S: Hackable FPGA that runs Linux on RISC-V

Being "simple" for a C program to decode is not the point; generating the smallest hardware to decode instructions and to reduce the critical path for things like deducing the instruction operands are.

For example, the operands all stay in the same position, which prevents putting decode on the critical path before you can figure out which registers you need to read (which is doubly important for superscalar designs which need to compute the register dependence graph). Likewise, the sign-extend bit for immediates is always in the same place, providing relief for another potential critical path.

_chris_on Kerbal Space Program 2 release disrupted by corporate strife

> The game had been set to come out this year [me: March 2020], but the company said last month it was delaying the release until the fall of 2021.

Is delaying the release by over a year and a half a win? I wonder how much in royalties/costs they're really saving.

_chris_on Why It’s So Hard to Create New Processors

Only speaking for myself, I think of FPGA and hw emulation interchangeably.

At the end of the day, I don't care (or know) how it's implemented. What I can say is a) they aren't super fast, only ~1Mhz b) they take forever to compile down to, c) they have some, but not great visibility to what went wrong, and d) they cost a stupid amount of money.

_chris_on Why It’s So Hard to Create New Processors

Great question. For starts though, you've just given me a list worth hundreds of trillions of instructions of tests.

If you can actually test on an FPGA (which is usually not possible, and if it is, it's not representative of the actual silicon/analog system you're building anyways), you can get 1T instructions in roughly ~6 hours at 50 MHz. But most hardware emulations are ~1 MHz, so now you're looking at weeks to hit 1T instructions (SPECint alone is 20T).

And what happens when you hit a bug, 2 weeks in? It may not be because you actually wrote new, buggy code, but because a new, higher performance branch predictor uncovered existing bugs. But you'll never know, because the FPGA historically gives you terrible visibility.

But in simulation (where testing is actually done), you're looking at ~1 Hz for a cpu core. Ouch. Obviously a better approach is required (unit-tests against models, formal, etc.), since at the level of detail you can't test much of anything.

_chris_on Why It’s So Hard to Create New Processors

> (B) I'm very much in a position where I can influence research in this direction.

Could you elaborate on what you do?

> Have you got any concrete ideas and proposals?

My recommendation is: try to build something complex, or take something from open-source that is very complex and extend it (test it, verify it, improve performance, etc.). Notice the problems you encounter, and then try to solve those problems.

I could give you a laundry list of pain points myself (why do I have to pay money for lint, and why does lint still suck???), but I think the best research is done by people trying to solve problem X, but along the way ended up having to solve Y and Z just to get to X.

_chris_on VHDL support for open-source FPGA toolchain YoSys

If you're willing to compromise on material, I believe Organic thin-film transistors (OTFT) can be patterned using printers!

https://en.wikipedia.org/wiki/Organic_field-effect_transisto...

Paper discussing characterizations and tradeoffs for designing processors for OTFTs:

http://parallel.princeton.edu/papers/micro17-chang.pdf

_chris_on What If C++ Abandoned Backward Compatibility?

My boss will never sign off on using a new language?

_chris_on Ask HN: Contingency Plans for COVID19?

Bought lots of frozen food and water (I should figure out how to do sugar water).

_chris_on Chris Lattner to Lead SiFive Platform Engineering Team

To add to what you said, a 64 bit ARM ISA didn’t publicly exist yet when Berkeley started RISC-V.

_chris_on Apple Sues Nuvia’s CEO, a Former Employee

I’m sure it’s also about setting a precedent to current and future employees regarding leaving and starting new companies.

What VC wants to spend their early money on lawsuits, even if you’ll (eventually) win?

_chris_on Myths Programmers Believe about CPU Caches (2018)

The wonderful thing about caches is that they are invisible to the programmer; the designer can add bigger caches, more levels of caches, different configurations of shared/private/inclusive/exclusive caches... and it Just Works.

However, there are many machines, which instead of using caches, use programmer-visible “scratchpads”. There are many reasons for this, but two big reasons are performance-predictability (real-time systems) or to avoid the hw complexity of cache management.

In general though, scratchpads are hugely painful to program for and terrible for code portability.

_chris_on SiFive Announces First RISC-V OoO CPU Core

When you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.

_chris_on SiFive U8-Series Core IP

AIUI, the U5 series is BSD/open-sourced as "Rocket", and a version of their shared L2 cache is available as the sifive-inclusive cache. I believe Berkeley uses these artifacts as part of their FireSim (https://fires.im) FPGA-based infrastructure.

_chris_on Anne Hunter Retires from MIT

End of an Era. She was incredibly helpful and kind in helping students navigate MIT and Course 6. It's going to take an entire department to replace her.

_chris_on Sipeed Longan Nano – RISC-V Development Board

You are confusing memory consistency with cache coherency.

_chris_on I Am the Cheapest Bastard in Indie Games

> "Cheap lo-fi art that looks good" is not a thing

Dwarf Fortress was literally an exhibit in MOMA; it can look downright beautiful, despite being nothing but ASCII letters in different shades of colors:

https://www.moma.org/media/W1siZiIsIjI1NTc0MSJdLFsicCIsImNvb...

_chris_on I quit my job today to make video games full time

Great to hear he did his homework!

Last I looked into this, AIUI, the default in the US is "everything the employee does the employee owns" (damn you wedding photographers!).

So naturally, virtually every tech company contract will have a "work for hire" clause which says "never mind that, everything the employee does the company owns (on or off the clock, in the shower, whatever, it's all ours)".

California adds an extra exception, which is "whatever the employee does (on their own time and equipment) that is 'unrelated to the company's business' is still the employee's." While that may safeguard my oil painting hobby, I'd always be nervous about any programming (game or otherwise) if I work for a tech company...

_chris_on A Look at the AMD Zen 2 Core

"Hashed" in this case simply means they did some extra work to deal with the perceptron's XOR problem, since a straight mapping of PC and branch history would led to an inability to distinguish XOR patterns.

_chris_on A Look at the AMD Zen 2 Core

First, most uops can't throw exceptions, so fusing a shift and an add instruction together doesn't require any complex tracking here.

If a uop throws an exception (let's say a fused add+ld), each uop can have a tag that helps you backtrace to its PC (instruction address) of let's say the start of the sequence, so you know what to inform the Privileged Architecture as to what "instruction" excepted. For many reasons, you need to store a list of PCs of the inflight instructions somewhere (although it is heavily compressed), so having a small ID tag to help reconstruct a given uop's PC isn't too onerous.

Ideally, multiple instructions may map to a single uop, but either none (or up to one) can throw an exception. The hard one here is something like load-pair uops; since each load can throw an exception. Some machines, if a fault is encountered, will refetch the pair and re-execute as independent/unfused loads. Other designs will just pay the pain of tracking which of the pair excepted and do some simple arithmetic off of that.

_chris_on RISC-V Vector Extension 0.7 by Krste Asanovic [video]

Designing a good vector ISA is really hard.

The problem is "vector" is an entire category of architecture-style and machine designs; it's not a problem domain. So some people want vector for their very narrow domain (ML? IOT?), and other people want vector for some other narrow domain (HPC? media?), and other people want it for "general-purpose" compute (whatever that means).

Hard questions: what data types do you support? Do you support mixed-types? Do you support expanding operations (64x64=128?)? Do you support reductions? How do you support conditional/branching execution? How do you support interrupts/exceptions? Do you support register file reconfigurations? How do you do function calls? Context switches?

Looking at the evolution of Intel's SIMD ISAs, they started from small 64-bit integer-only multimedia stuff (MMX), and are now at AVX's 512b masked execution with scatter/gatters and exponentials and reciprocals... there's a lot of complexity you can add to a vector ISA. :0