fooblaster

coming back in one piece, and being good enough to use for 5 more missions are two very different things. For example, all existing reentry vehicles come back "fine" but they need to be completely remade to go up again.

"surviving reentry" and being reusable are two very different things, particularly if this is to become human rated.

You know a whole the size of a quarter can wreck the entire spacecraft and make it effectively throw away? Also, you'd want to use this many times. Making a system robust while not requiring months of refurbishment is really really hard.

The hardest problem in the entire design had yet to be solved. Having a robust human rated tile system that can be rapidly turned around is a huge engineering challenge that kind of breaks the whole point of the design if it doesn't work. I wouldn't be surprised if they eventually give up and go back to a cheaper throw away second stage, or throw out the tile design completely and try for some evaporative cooling approach, again.

what research? it's private and there is large incentive to lie until ipo

so speculation from a semiconductor website. that's incredibly likely to be wrong

how exactly can you assume they have unit profitability

All major silicon companies use something quite different. Not FPGAs, but significantly faster than software (500khz cycle times instead of 200mhz).

https://www.cadence.com/en_US/home/tools/system-design-and-v...

They cost an absolute fortune but they pay for themselves very quickly when you catch a bug you would have found on your first silicon spin.

Airlines can't raise the prices of tickets sold months ago. There is still financial reason to hedge.

I think the revenue claims around future trainium spend is complete bullshit.

Honestly, this is the AI software I actually look forward to seeing. No hype about it being too dangerous to release. No IPO pumping hype. No subscription fees. I am so pumped to try this!

Tesla has not pulled the driver. It's just not comparable.

It's fine to not be interested, but this time one of the astronauts is black

where are you? that is a massive amount of solar in any place at a reasonably low latitude. Is your house enormous or are you heating your house with resistive heating?

This thing is far from over. Iran will indefinitely be able to block the straight. The us will be stuck in this defensive position for months, until it pulls out and effectively loses the war.

It's clear we are going to lose, because we cannot topple the regime without putting troops on the ground, which we will never do. Setting that as a war aim doomed this whole effort from the start.

what inference runtime are you using? You mentioned mlx but I didn't think anyone was using that for local llms

Again, it wasn't exactly a huge sink of resources. There was no genius gamble from jensen like you are suggesting. I suspect your view here is intrinsically tied to your need to feel like you and others who are in your position are responsible for your own success, when in fact it's mostly about luck.

CUDA was profitable very early because of oil and gas code, like reverse time migration and the like. There was no act of incredible foresight from jensen. In fact, I recall him threatening to kill the program if large projects that made it not profitable failed, like the Titan super computer at oak ridge.

It was definitely luck, greg. And Nvidia didn't invent deep learning, deep learning found nvidias investment in CUDA.

I was really happy to see that blue spec was fully open sourced in recent years. Does anyone have experience with a non trivial project with it? Does it have any traction anymore in real silicon development.

calling neural engine the best is pretty silly. the best perhaps of what is uniformly a failed class of ip blocks - mobile inference NPU hardware. edge inference on apple is dominated by cpus and metal, which don't use their NPU.

Looks like they have made some progress on a native model in recent months: https://github.com/amd/IRON/tree/devel

sms is the Nvidia definition of processor, and cuda device properties returns it, not anything else. If you want a marketing number, use cuda cores, it doesn't consistently match to anything in the hardware design.

b200 is 148 sms, so no

The versal stuff isn't really an FPGA anymore. The chips have PL on them, but many don't. The consumer NPUs from AMD are the same versal aie cores with no PL. They just aren't configurable blocks in fabric anymore and don't have the same programming model. So I'm not contradicting myself here.

That being said, versal aie for ml has been a terrible failure. The reasons for why are complicated. One reason is because the memory hierarchy for SRAM is not a unified pool. It's partitioned into tiles and can't be accessed by all cores. additionally, access of this SRAM is only via dma engines and not directly from the cores. Thirdly, the datapaths for feeding the VLIW cores are statically set, and require a software configuration to change at runtime which is slow. Programming this thing makes the cell processor look like a cakewalk. You gotta program dma engines, you program hundreds of VLIW cores, you need to explicitly setup on chip network fabric. I could go on.

Anyway, my point is FPGAs aren't getting ML slices. Some FPGAs do have a completely separate thing that can do ML, but what is shipped is terrible. Hopefully that makes sense.

10 MB mail app. 690 MB local llm to write snarky emails for you.

wow, say more..

I'd like to know more. I expect these systems are 8xvh1782. Is that true? What's the theoretical math throughput - my expectation is that it isn't very high per chip. How is performance in the prefill stage when inference is actually math limited?

This architecture is likely going to be a dead end for AMD. It has been in the wild for several years, yet still has no open programming model, multiple compiler stacks with poor software support. I find it likely that AMD drops this architecture and unifies their ML support around their GPGPU hardware.

The amd npu and versal ML tiles (same underlying architecture) have been an complete failure. Dynamic programming models like cu tile do not work on them at all, be cause they require an entirely static graph to function. AMD is going to walk away from their NPU architecture and unify around their GPU IP on inference products in the future.