matja

Can you elaborate what is silly about it? The reversing, or the DNS, or both?

A package called com.example.foo would be package foo in the namespace "example", which is under the namespace "com", which is how a lot of languages do namespace nesting.

DNS can be said to be "reversed" from that point of view.

FDE doesn't prevent TRIM, but the dm-crypt implementation defaults to disabling TRIM because it has theoretical security consequences. The option to enable it was introduced in Linux 3.1 (2011)

It was ever?

Just poking some registers to send an Ethernet frame kind of hand-waves all of the ACPI table lookup, AML parsing, PCIe root/bridge init, etc, so in that regard "mov dx,0x3f8 ; out dx,al" is more simple and reliable - USB needs all of the same PCI/PCIe stack also so is of course a nightmare :)

Wasn't it the devices which used FTDI FT232/233/2232/2233/4232/4233 device VID/PIDs that they targeted?

DNS is only as stale as the cache that you trust. If the cache is not adhering to DNS standards then it is probably not one you should be trusting. Nothing is stopping a DNS client contacting the authoritative nameservers without a cache, or using your own cache that implements the standard correctly.

I was just thinking this looks similar to a DDI (Data Documentation Initiative) citation element, but the advantage of the DDI XML schema is that one can annotate any existing element in an XML document by importing the DDI namespace, which shouldn't change how the document is otherwise interpreted by applications, but this JSON schema as far as I can tell is a stand-alone document?

> JSON numbers are also 64-bit floats

In common implementations they are, but RFC 8259 and ECMA-404 do not specify the range, precision, or underlying implementation for the storage of numbers in JSON.

A implementation that guarantees interoperability between all implementations of JSON would use an arbitrary-sized number format, but they seldom do.

No idea what ISO/IEC 21778:2017 says because it's not free.

> The amount of RAM you were allowed to plug into a PC motherboard always felt like the most annoying limitation

You could always get motherboards that took more RAM, just not ones that taking your typical gaming CPUs and RGB. Currently there are standard desktop-sized ATX motherboards that take 3TB of DDR5, and ATX boards that take 1TB of DDR4 have existed for years.

GL_ARB_texture_env_dot3 was implemented on the Geforce 3 launched in 2001, but the GeForce 256 launched in 1999 had dot3 support

add: | numfmt --to=iec

The 120k+ lines of code in drivers/tty/serial in Linux suggests that maybe it's not _that_ trivial.

Yes every hypervisor has this "feature" unless it uses CPU features to protect memory, such as encrypted VM memory available on newer AMD CPUs (SEV) : https://www.qemu.org/docs/master/system/i386/amd-memory-encr...

The big cache version of the Pentium Pro (512kB) was 1,217 USD (1996) - 2320 USD (2023) with inflation.

Another fascinating Neutron star life story : https://en.wikipedia.org/wiki/Flux_(novel)

> but how would one get access to an IBM zSeries?

qemu-system-s390x - I run Linux in it for some automatic tests, finds some funny bugs occasionally.

From memory a 486DX4-100 or an overclocked 486DX2-66 (to 80MHz) could just about handle 128kbit MP3s

Except "evenly" is not a standard, or something that anyone other than the manufacturer can verify, it's hidden in the firmware so we have no idea really.

Was there any hardware/software which actually did this?

I can't think of any games console hardware which allowed a combination of more than two shears by modification of sprite/bg offset registers, it was either X, Y, or X+Y, but not X+Y+X.

It seems to me that using dx+dy 8.8 or 16.16 fixed-point coefficients for an inverted rotation matrix would by faster in terms of only one read+write required per pixel, rather than multiple (at least that's how I always saw rotations in the VGA mode 13h days, maybe things like the Amiga blitter could do it better?).

IMO because you can configure the BMC to use it's own dedicated NIC and network.

That network should have no routing to the Internet and no production traffic, just BMC management.

When Intel ME shares the NIC used for the OS traffic - that is far harder to secure.

I hoped this would explain the anomaly in AMD EPYC 3rd gen Milan pricing for the 24 core "F" (frequency optimized) parts being cheaper than the 16 core ones, but I still can't see any hint to the reason:

    model  | cores | price |
      73F3 |    16 | $3521 |
      74F3 |    24 | $2900 | <- cheapest
      75F3 |    32 | $4860 |

Same for 4th gen Genoa :

    model  | cores | price |
     9174F |    16 | $3850 |
     9274F |    24 | $3060 | <- cheapest
     9374F |    32 | $4850 |

The 24-core parts have the same number of CCDs, and thus same total L3 cache, and a higher turbo than the 32-core parts.

Why is that surprising? It is a difference license. So is the Nvidia driver.

CRIU (https://criu.org/Usage_scenarios) can be used to speed-up spawning processes or duplicating state, can save significant time.

4? Chrome OS, Android, Qubes OS, Linux

seems piping through `iconv -f utf8 -t macintosh` fixes them

I understand the rationale of having a relatively simple filesystem specification so that it can be implemented under the constraints of embedded systems, but using a filesystem that has no journal or checksums on the cheapest and flakiest of storage devices (hi, bottom-of-the-barrel SD cards and USB memory sticks) seems a recipe for disaster in terms of data resiliency.

I use ZFS on SD cards and USB memory sticks when I am able to, and the number of checksum errors are ... not rare. Even for high-quality NVMe SSDs on (lower quality) USB-NVMe bridge controllers, corruption everywhere.

If you don't have a lightbox, a long exposure (15-30 seconds, might need a very small f-stop or ND filter) and waving an LED torch around the PCB is almost as good at removing all the shadows, but less consistent.

Ryzen 5xxxG(E) or Ryzen 5 5500 -> Cezanne

Ryzen 5xxx -> Vermeer

Threadripper 5xxx -> Chagall

EPYC xxx3 -> Milan

> The First Digit bears no connection to anything

One pattern is: If first digit is 3,4,5 then it has one AVX512 FMA unit, if it is 6,7,8 then it has two.

...except the 5122 (2), 5219Y (2), 5222 (2) and 6122 (1)

addl is not necessary if it is not ambiguous

    add $4, %eax

- is fine

Compare with

    add 4, %eax

The "less noisy" Intel syntax becomes:

    add eax, DWORD PTR [4]