- Lots more speed cameras
- Average speed cameras especially make a huge difference vs spot enforcement
- Tolerance for enforcement is normally 10% rather than 10 mph (i.e. 30 limit means no more than 33mph rather than no more than 40mph)
542 karma · joined April 21, 2021
- Lots more speed cameras
- Average speed cameras especially make a huge difference vs spot enforcement
- Tolerance for enforcement is normally 10% rather than 10 mph (i.e. 30 limit means no more than 33mph rather than no more than 40mph)
For the uninitiated, most high-performance CPUs of recent years:
- Are massively out-of-order. It will run any operation that has all inputs satisfied in the next slot of the right type available.
- Have multiple functional units. A recent apple CPU can and will run 5+ different integer ops, 3+ load/stores and 3+ floating point ops per cycle if it can feed them all. And it may well do zero-cost register renames on the fly for "free".
- Functional units are pipelined, you can throw 1 op in the front end of the pipe each cycle, but the result sometimes isn't available for consumption until maybe 3-20 cycles later (latency depends on the type of the op and if it can bypass into the next op executed).
- They will speculate on branch results and if they get them wrong it needs to flush the pipeline and do the right thing.
- Assorted hazards may give +/- on the timing you might get in a different situation.
However, we still end up writing different code for different target SOCs, as the microarchitecture is different, and we want to maximize our throughput and take advantage of any ISA support for dedicated instructions / type support.
One big challenge is targeting in-order cores the compiler often does a terrible job of register allocation (we need to use pretty much all the architectural registers to allow for vector instruction latencies), so we find the model breaks down somewhat there as we have to drop to inline assembly.
They'd rather make capital investments (which aren't a recurring budget line, so the same money can make different headlines next year) than pay for the sort of ongoing spend on paying experts competitive salaries to actually build a real capacity.
Prior to Turing Institute there was the Hartree Centre, which was hobbled from hiring anyone significant by being tied to a non-technical civil-service payspine that struggled to approach even "competent" level salaries for these positions as the posts didn't manage 100s of minions.
Richer customers self-select to pay higher prices without the app as they can't be bothered faffing around to find the digital coupon/deal/whatever combination (you can, of course, only use one of the wide range of deals at a time). Poorer customers will invest the time in finding and using a deal.
They both get the same sandwich, but McD got them to pay different prices for it.
But maybe that's a peculiarity of the numerical algorithm performance space I live in, where debugging the numerics of a fully parallelized and vectorized algorithm with all sorts of performance bells and whistles, inline assembly and accelerator usage is much much more difficult than fixing the bug in simple scalar C code.
You end up with "Computer says shoot" and so many cooks involved in the software chain that no one can feasibly be held accountable except maybe the chief of staff or the president.
The most recent moves seem to be relaxing the pricing rules to allow major disaster pricing and recharging reinsurance rates in exchange for insurers offering more policies in high risk areas.
Everyone else basically had to reformulate their research to pretend it was applicable to the government's funding subject de jure. This led to some quite large stretches in definition to achieve "<Main area of research>, and some applications in <funding stream>". This very much felt like it was sucking up to money.
I got out of the academia in the end because it felt like the more senior I got the more time I spent applying for funding and managing the spending and the less time I spent doing research/development. (Also given I was in a UK public sector institute, the pay was shit due to 40 years of below inflation pay rises crippling the institution).
CPUs aim to minimize latency (how many cycles have to pass before you can use a result), and do so by way of high clock frequencies, caches and fancy micro architectural tricks. This is what you want in most general computation cases where you don't have other work to do whilst you wait.
GPUs instead just context switch to a different thread whilst waiting on a result. They hide their latency by making parallelism as cheap as possible. You can have many more cores running at a lower clock frequency and be more efficient as a result. But this only works if you have enough parallelism to keep everything busy whilst waiting for things to finish on other threads. As it happens that's pretty common in large matrix computations done in machine learning, so they're pretty popular there.
Will they converge? I don't think so - they're fundamentally different design points. But it may well be that they get integrated at a much closer level than current designs, pushing the heterogeneous/dark silicon/accelerator direction to an extreme.