ynoxinul

A manchester-encoded bit 1 is a low-to-high transition: there should be "low" on the line which will change to "high". Before the "low" the line was idle (zero voltage difference), this state is interpreted by the differential amplifier as "high", so it's "high-low-high" at the beginning, but we are interested in the "low-high" edge and not in the "high-low" one.

The preamble is intended for synchronization, the last two consequtive ones indicate the start of the data.

My circuit doesn't drop any frames, it simply converts serial Ethernet signal to SPI. FCS and MAC checking is done in software after receiving the whole frame.

You absolutely can get frames not addressed to you. Wireshark lets you do that. I debugged my adapter this way: I connected it to a dumb switch together with my computer and ran Wireshark on the computer which captured all frames regardless of their intended destination. On Linux you can even disable FCS checking and receive all rubbish from the wire.

Do you think they are worth mentioning? My post isn't a tutorial.

Yes, but this is only the case with 10BASE-T. Modern standards use more complicated Fast Link Pulses.

Thank you, fixed.

It's a fun project. I feel like building stuff with logic gates.

Thanks, fixed it.

The preambles were longer by a few bits (even less than 8). I didn't check which frames excatly caused this, but it happened only with one old 10 MBit switch.

I used Falstad curcuit simulator (https://www.falstad.com/circuit/circuitjs.html) to try out some subcircuits (monostable, for example) and then tried them out on a breadboard.

Looks interesting. How are closures implemented? Is it possible to use Ante without heap? Are function arguments passed by value?

I'm a Russian in Germany. I've fled Russia after Crimea/Donbass events because of Putin's politics. No Russian I know in Germany or any other country abroad supports Putin.