VHDL is really verbose compared to Verilog. Some people love that verbosity, but I prefer to see more "action" in a screen of code.
entity ForInpAndGate is
port( a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
o: out std_logic;
);
end ForInpAndGate;
architecture behavioral of ForInpAndGate is begin
process(a, b, c, d) begin
o <= a & b & c & d;
end process;
end behavioral;
Let's hope the community shows some interest in my efforts to make this library the best of both worlds - verbosity with action :P
But one of the reasons might be because I would like the person going through my code to easily understand it without much problems.
It's more about perspective I suppose and the requirements of the project.
Can you provide some reference link to systemVerilog?
http://standards.ieee.org/getieee/1800/download/1800-2012.pd...
There is an open source compiler which can compile the hardware description subset of system verilog to c++ called verilator:
http://www.veripool.org/wiki/verilator
It was originally developed to verify processor designs at DEC (Alpha etc.).
Unfortunately all the other features of system verilog are onl y implemented in commercial tools. I believe the Xilinx Vivado tools support most of it, the others are not really affordable if you are not at an academic institution (Modelsim/the Synopsis tools).
Thanks for the references though!