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Comment by adapteva | Hacker News Reader

Not going to happen in the near term. There is no way to meet the price point needed to compete in the low cost SBC market with the Epiphany-V. Believe it or not, the $99 Parallella was priced too high to reach mass adoption.

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How about a evaluation board which plugs into the mezzanine connectors of the ZC706 evaluation kit? Something similar to the AD9361 FMCOMMS3/5 [1]

Also: any more information on the ISA extensions for communications/deep learning?

[1] https://wiki.analog.com/resources/eval/user-guides/ad-fmcomm...

Sure, there will be evaluation boards, they just won't be generally available at digikey and won't cost $99. More information about custom ISA will be disclosed once we have silicon back.

Having seen that the $99 price point was too high, is one of your goals still "supercomputing for everyone"? Or has that dream been dashed?

Well, the Parallella has shipped to over 10,000 people and it still selling at Amazon an DK, so no the dream is not dashed in any way. The number of publications and frameworks around Parallella is growing every month...

No reason to drive a 1024 core chip to the broad market when most applications aren't ready to use 16 cores. With this chip we focus on customers and aprtners who have proven that they have mastered the 16-core platform.

>No reason to drive a 1024 core chip to the broad market when most applications aren't ready to use 16 cores.

Yet magically they have no problem taking advantage of massively parallel GPUs...

Most applications don't use 16 CPU cores because they don't need them.

I think you're underestimating the requirements and mastery of cloud companies. Something like an Amazon lambda could virtualize 4 cores per instance and host 256 lambda execution units on a single chip. The use cases are endless

Unless the architecture has changed drastically from the earlier Epiphany, they can't be virtualised like that, and each core are way too slow to be suitable for lambda except for software written specifically to take advantage of the parallelism of the architecture.

You still need to recompile code for the new architecture, and taking full advantage of it wisely is not easy... but may be worth it in many use cases. Part of the problem is that it's not 100% clear which use cases these are and how to market it. Probably unit calculation per watt is the most likely performance advantage, but it's still amazingly hard to sell people on that sometimes

Some parallel algorithms will scale to bigger (more parallel) chips the way binary programs got more performance with clock higher frequencies. That's the holy grail..

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