This is called Data Scrambling on Intel processors. There's not a lot of info I can find from the horse's mouth, but the datasheet [1] has a blurb:

    The memory controller incorporates a DDR3 Data Scrambling 
    feature to minimize the impact of excessive di/dt on 
    the platform DDR3 VRs due to successive 1s and 0s on 
    the data bus. Past experience has demonstrated that
    traffic on the data bus is not random and can have 
    energy concentrated at specific spectral harmonics 
    creating high di/dt that is generally limited by data 
    patterns that excite resonance between the package 
    inductance and on-die capacitances. As a result, the 
    memory controller uses a data scrambling feature to 
    create pseudo-random patterns on the DDR3 data bus to 
    reduce the impact of any excessive di/dt.

So basically, all the kernel knows is that the data is in there "somewhere", and can be accessed traditionally.

[1] http://www.intel.com/content/dam/www/public/us/en/documents/...