Designing hardware is done by Visio and Excel not Verilog.
Verilog is just an implementation. :)
Added: Visio is to draw timing diagram, block diagram, and flow chart. Excel is used for designing FSM next state logic / output.
Added: Visio is to draw timing diagram, block diagram, and flow chart. Excel is used for designing FSM next state logic / output.
You need to prove that you can get a certain performance with a matlab algorithm, then you spend a week writing it into verilog.
Oh, and as someone whose bread and butter is ICs, I go out of my way to avoid creating FSMs. They're slow, difficult to debug, and hard to pass on to your successor.