I'll have to repeat my question in other words. How many MIPS do you think, remain, if every third instruction is a mispredicted branch and every second memory access is a cache miss?

Modern CPUs use pipelining which executes many instructions parallel. This only works well if everything goes as predicted. If you have an algorithm which works contrary to what the branch prediction thinks and a cache which does not hold the data you need, your performance goes down the drain. Those MIPS mean nothing if not put into the right context.