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Comment by akuma73 | Hacker News Reader

Have a look at this photo: http://m.eet.com/media/1169843/120906_intel_22_3.jpg

That's a fin of a modern transistor (Intel 22nm). The dots in the photo are atoms. It's fair to say that Moore's law is nearing an end or has already ended.

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Atoms are too big, photons are too big, electrons are too big, and the speed of light is too slow. There's no longer plenty of room at the bottom.

Still, it's not like the physical size of semiconductors is the problem. A CPU today is maybe 100mm^2 of silicon. 4U of rack space can easily hold tens of thousands of CPUs, if you can power them, cool them, and connect them up in a useful way.

if you can power them, cool them, and connect them up in a useful way.

Good luck with that. Power costs go up linearly at best with cores if you don't have any more transistor scaling.

Power will always scale linearly with cores, of course, but you could make cores less power-hungry with reversible computing: https://en.wikipedia.org/wiki/Reversible_computing

Actually useful reversible logic is, as they say, an open problem.

My point was that a new transistor shrink would give you lower power vs. the same transistor in previously larger node. You get more compute-per-watt with small transistors. If scaling stops, then all kinds of things get more difficult.

I have heard that Electrons move about a millimeter second (although electromagnetic emanations propagate at the speed of light). This is allegedly the benefit of 'optical' computing.

Not quite.[1] Propagation in most interconnects is about half the speed of light, because real-world wires have capacitance. (As low as 25% for CAT 5 cable, as high as 90% for open-wire antenna feeds.) Optical fiber runs about 70% of the speed of light. On-chip interconnects run 30%-60% of the speed of light. So there's some propagation delay improvement with optical interconnects, but it's a factor of about 2, not some huge improvement.

[1] http://www.edn.com/electronics-blogs/all-aboard-/4426188/Rul...

Think outside the box. Current chips have gates on a dozen metal layers measuring ~1µm, but you could scale to 10,000 layers at ~1mm. Sure there are many unsolved challenge to build 10,000 layers, but there is still PLENTY of space for Moore's law to continue in this 3rd dimension...

I assume you mean stacking transistors? This has been tried, and there are serious thermal issues. Where does the heat go in the intermediate layers?

If you could solve both the heat dissipation and yield problems that 3D chips have you would be a very, very rich man.

People said similar things when we reached the wavelength of visible light.

Yes but that was a cost and engineering issue. The size of atoms is a lot more fundamental. EUV buys you a little more but you still bump into the size of atoms and quantum effects pretty quickly.

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