We are not only concerned by FPGA but also CGRA (developping our own: Plasticine). For FPGA, we target Chisel. Chisel is Verilog without the boilerplate. We aim to be more high-level by generating also all the control flow.
I've always been wary of inference-based systems that target clocked logic. Most of them (especially the C-based ones) are not suited to produce efficient designs and usually require some heavy massaging of the original code to make the inference system happy.
The designers of Chisel don't speak the same "language" as your average hardware designer. Maybe this is why people have invested tons of hours to re-write risc-v in pure verilog [1] and VHDL [2].
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