Yes, storage for example isn't on the SoC, so bus speed will limit storage speed.
It seems like we'll be sticking with PCIe x4 interfaces for SSDs for quite a while; client/consumer use cases don't allow for higher pin counts, and at the moment there's not much reason to prefer using half as many SSDs with twice the lane count for enterprise storage, especially when it means none of the parts can be shared with the client/consumer ecosystem.