For those that want to read the original BOOM paper first, I'll save you a bit of time: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-...
Fair enough, you didn't reach the same frequencies, but that's what the other 1.4mm² and the process shrink are for.
ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right?
Update: also probably SIMD[or vectors], breakpoints, more interesting memory management, the handling of bizarre FP corner cases, maybe power management[high frequency dvfs? :- )], and other things go in that additional 1.4mm².
O:-)
> ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right?
Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318
Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.
> Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.
Yeah, I drew my conclusions from your papers. :- )
I really should diversify my sources, I bring nothing to this exchange.
Also there's no current RISC-V extension for SIMD or vector ops, so I didn't maliciously "omit" things to "totally rig" the comparison. But even running SPECint is not going to fire up the SIMD unit.
SPEC with modern compilers will definitely use SIMD, utilization on hot regions is variable but it's definitely beneficial.
Models with FMA: Cortex-M4, Cortex-M7, Cortex-A5, Cortex-A7, Cortex-A15, Cortex-A17. I do not remember which Cortex-R have FMA. Models without FMA: Cortex-A8, Cortex-A9.