Not much. Clock wall, power wall, and latency wall are here.

The only thing improving is memory size, bandwidth, and number of cores.

Now, we are still very far off from every worload being at its theoretically maximum throughput (that would be achieved with an ASIC).

Over the next years, the interesting things won't come from Intel or AMD. The generic processor killing all competition has reached an end. Intel could just wait till the next technology node to thwart off any attempt of adapting to a corner of the market. This is no longer the case; with so much money at stake, expect a Cambrian explosion.

It will come from specialized workloads getting an accelerator (think integrated TPUs, NICs with FPGAs, etc); it will come from tighter chip packaging/integration (think close-access DRAM a few μm from the CPU with silicon vias, early filtering with predicate pushdown directly into the SSD controller, etc.).

Now, the code will have to adapt; and I posit that the languages better suited for this should have:

* An easy way to control the memory layout

* An easy way to insert special-purpose instructions

* A compiler infrastructure flexible enough to be able to coerce code into the accelerators

* An easy way to serialize (possibly half-executed-)code that should be transported closer to the data