> Only thing that matters is waffer price, yield, transistor count and TDP.
Wouldn't 5 nm allow shorter wire traces, which would reduce another limiting factor in computational speed?
Wouldn't 5 nm allow shorter wire traces, which would reduce another limiting factor in computational speed?
The fundamental limit of clock speed is power draw. As clocks increase the wattage ~ frequency relation goes from
frequency = Constant * Power Draw
frequency = Power Draw * Power Draw
Packing things in more tightly lets you spend less time in transit, which might let you squeeze more gates into a cycle, or do the same things a little faster.