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Comment by mjevans | Hacker News Reader

Wow, that's really small, and also really close to the theoretical limits (I recalled and thus looked for confirmation of that memory).

It seems like moving past 5nm is going to be... a lot differnet.

https://en.wikipedia.org/wiki/Nanowire

(edit to add) Nanowire is mentioned as the next likely node after 5nm on that article, but it doesn't link back: https://en.wikipedia.org/wiki/5_nanometer

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Don’t conflate “effective feature size” (the 5nm used in this article) with “real” feature size (or, more importantly, pitch), with transistor size. Transistors are still huge compared to atoms—think hundreds of thousands, or millions. The issues at this scale are all electrical. (Bullshit terms like “quantum tunneling” are bandied about; the scientific use isn’t wrong, but any journalist using the term probably is.)

There’s alot of room down there, below the extended Moore’s law, just not always so CMOS-ey.

Could you elaborate, what does “effective feature size” mean in the context of process technology?

It's my personal way of politely saying "marketing bullshit". The real importance of 5nm vs. 7nm is the density of the transistors. A large portion of the recent gains in transistor density have been from reducing the pitch (the space between) transistors, rather than shrinking the size of the transistor.

Ah ok, that's quite funny. Does pitch reduction result in performance gains indirectly though - more transistors per chip?

That's an ultra-qualified "yes". Hardware isn't magic. Once you've got a Turing-complete device, software can cover the rest. However, HW implementations of functionality are 'better' than software in the sense of being either faster or more power-efficient. (Or some trade-off.) Our chips are better because we can throw more customized hardware to side-step (slow; power-hungry) software implementations. We have access to more customized HW because we have more transistors.

If you're asking long-run questions in terms of HW/SW stack performance, I strongly suspect we've got another 3-10 doublings with "just more HW". If any of the post-patterning mechanisms pan out we could, theoretically, get another 15-20 doublings by going all the way down to atoms. After that ... I dunno; sort of the realm of scifi at that point.

Thanks that all makes good sense. I was curious about "post-pattering mechanisms"? Is this a new area in fab process technology? Might you have some links? Another 15-20 doublings from where we are today is pretty awesome.

Patterning is the use of multiple masks to get fine features smaller than the wavelength of light you're using where in previous larger feature nodes one mask sufficed: https://en.wikipedia.org/wiki/Multiple_patterning

It's very expensive in terms of tooling, since you need a lot more more masks, and production time spend in lithography steps. See this comment in this discussion https://news.ycombinator.com/item?id=19570724 for a bit more.

So does “effective feature size” mean anything?

Besides that 5 < 7.

My understanding is that in the old days of planar transistors it had a clear meaning but with modern designs not so much.

Interestingly, the semiconductor industry has thought it was close to its theoretical limits since feature size was measured in microns 40 years ago. Back then, one of the big worries was that we were approaching the wavelength of light used in the photolithography process and that there was no clear path to getting below 1000 nm. I expect that it will always be difficult to see beyond a few years of innovation in this area. It certainly does seem that we will soon need to switch to other materials and forms of signal transport though.

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