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Comment by kevin_thibedeau | Hacker News Reader

Cyclone outclasses any ICE40 out there. If you need the logic capacity or peripherals your options become constrained. The sad thing is that we had cheap Spartan-3's and Spartan-6's with impressive resources but the vendors didn't want to keep making devices with that sort of bang for the buck.

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The open tools also work on ECP5, which goes quite a bit bigger than the Cyclone 10 chip on the Arduino and is also pretty cost effective. In fact it's big enough that you can usually dispense with the separate microcontroller - I built a ulx3s which can boot Linux on the ECP5-85.

You can still buy Spartan 3 and 6 devices - last I checked they're even still being manufactured.

The tooling is not supported with bug fixes.

Another strike for Xilinx tooling then. Open source tooling can't come soon enough.

Same open source discussion again. I’ll try to explain short why it will never happen. Since FPGAs have applications outside hobbyist domain, things are getting complicated. There are lawyers involved, support contracts signed and vendors are liable for their silicon. Now imagine some open source toolchain is used and some problems occur. Who’s liable? No single vendor will invest a penny into something maintained by somebody else. No single manager on this world will allow me to use 3rd party tools without vendor’s support for €1M FPGA design. There is no business case for silicon vendor to open source anything. Maybe brave hackers will reverse engineer bitstream generation, but this knowledge will be used only among hackers and their friends. Personally I don’t see any advantage using these tools and writing this in my resume, because nobody will use them in industry anyway.

> Maybe brave hackers will reverse engineer bitstream generation

As far as I know, the bitstream for 15K/35K/50K Artix-7 is pretty much done, with Kintex-7 and Zynq devices being WIP [1]. I think there are gaps in support for the various hard blocks and PAR at higher layers of the toolchain, but the bitstream reverse engineering per se isn't a maybe-in-the-future thing.

[1] https://github.com/SymbiFlow/prjxray

You could surely have said the same about commercial software libraries 10 years ago.

> There is no business case for silicon vendor to open source anything

There is no good business case for the smaller vendors to develop and maintain a full set of very complex software either.

Xilinx gives away access to a multi-language license for Vivado, fully capable for all chips under hundreds of dollars, with a built in simulator (again, mixed language!) used by tens of thousands of actual hardware engineers around the world successfully, but they're the bad guys?

And their "unsupported" tool is also used successfully today by rafts of actual hardware engineers, and it's still better than the free alternatives by leaps and bounds.

There are no plucky garage shops or "wise crowds" making FPGA tools that are even in the same galaxy as ISE or Vivado.

> There are no plucky garage shops or "wise crowds" making FPGA tools that are even in the same galaxy as ISE or Vivado.

Symbiotic EDA comes to mind. However, I would argue they don't need to be great, just good.

I don't have a copy of Vivado to hand (I have an Altera dev board instead), but I can take PicoSoC with Yosys/nextpnr and have a bitstream in about a minute. If I try the same task in Quartus, that takes about five minutes. Producing a (relatively) inefficient bitstream actually speeds up the compile/run cycle in that scenario.

If the design meets timing, which is often decided by external factors, any extra time spend trying to make the design "better" is wasted time.

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