Scaling will continue in conjunction with packaging, but whether that’s Moore’s Law is debatable. The economics of traditional shrinking are gone. It now costs more per transistor at each new node. And the power/performance improvements have sharply diminished from pure scaling, probably into the range of 10% to 15% versus 30% to 50%. However, by combining architectural improvements (neural nets, moving memory closer to processors and vice versa, faster interconnects) and by stacking memory on die or embedded them in the same package, it’s possible to achieve orders of magnitude improvements in performance and power. This has been called More than Moore, and TSMC is now calling it More Moore.