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I don't see why not.

If you define an FPGA as taking a bitstream configuration input, then you'd have to write (in Verilog) an engine to interpret that input and configure some LUTs and routing switches. Routing switches are efficiently implemented in an FPGA, but emulating one might require hundreds of other switches. So it's going to be very inefficient.

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Interesting! I ask the question from a theoretical standpoint only. Yes, it would be slow if it was done, no question about that! But maybe it could find use as a way of testing/validating a correct HDL FPGA design before manufacturing actual hardware...

Many ASICs are tested as 'soft' designs on FPGAs before becoming ASICs, which is essentially the same idea. It is a lot faster than verilog simulators.

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