I used Chisel to make a relatively simple memory encryption engine AXI component for FPGA. In my experience, the typedness and composability of Modules makes it significantly more productive than directly writing Verilog. There's an escape hatch, too: interfacing with vendored IP and hard macros is straightforwrd using `BlackBox` (DI is useful for mocking these in tests). My only wish is that Scala properly supported macros.

One of my favorite components of the ecosystem is https://github.com/ucb-bar/chisel-testers2, which replaces the peekpoke tester and makes it easier to test asynchronous IO.