ie. anywhere that describes the segment base, limit, and permissions on a separate privileged table.
I wonder why.
<<<According to the New York Times, "the i432 ran 5 to 10 times more slowly than its competitor, the Motorola 68000" >>>
https://en.wikipedia.org/wiki/Intel_iAPX_432#The_project%27s...
From memory a quote from a user of it, something like: "on a good day it walked, on a bad day it crawled"
IIRC every main memory access needed 3 pointer derefs and 3 array lookups (from memory).
There are ways to make page table swapping cheaper. E.g. SPARC and S390 always had separate page tables for user and kernel space, with an "ASID (address space identifier)" to avoid having to flush them when switching.
I believe decently modern x86 CPU's also have this in the form of "PCID".
Are you serious and are you talking about x86 memory segmentation? Honest question. As far as I'm concerned thinking about CS, DS and ES still gives me shivers and I don't remember to ever have met anyone back then who loved segmentation. The only thing I hated more was the bit planes stuff on the graphics card...
This wasn't defined by Intel, but Windows went on to depend on this feature in order to boot (to access PCI)
(I was once involved in an x86 clone project)
> Half the issue with Spectre is that there isn't a clean way to describe to the processor different memory security contexts except with a page table pointer swap.
You don't need segments for that. A flat address space where the 2 MSBs (or however many you need) of a pointer encode the context would also work.