I wish someday we'll get something like the ESP32 boards but with RISCV.
I wish someday we'll get something like the ESP32 boards but with RISCV.
You might want to check out the Kendryte K210. I'm trying out these boards for development. They are designed with two (I think) 64-bit RISC-V cores with a hardware FPU. https://www.seeedstudio.com/blog/2019/09/12/get-started-with...
I've flashed mine a few times, but I'm still working to getting it to work. The documentation isn't very good, so I'm working to reverse engineer some aspects of it.
This is a low cost alternative. Of course, we could go with the SiFive Unleashed (64-bit) or the SiFive HiFive1, which uses a 32-bit RISC-V CPU in an Arduino form factor. https://www.sifive.com/boards
The SiFive Unleashed cost me a cool $1k, so I'm still scared to mess with it.
The most interesting route is using an FPGA. There are many examples of running RISC-V softcores on FPGAs (for example, Berkeley's RocketChip) and many boards that support a decent amount of memory (even beyond 1 GiB).
I looked at the Xilinx FPGAs--the ones SiFive recommends, but they're quite pricey.
Which FPGAs had you had luck with?
1. https://www.crowdsupply.com/1bitsquared/icebreaker-fpga 2. https://www.crowdsupply.com/radiona/ulx3s 3. https://groupgets.com/campaigns/710-orangecrab
https://www.seeedstudio.com/Sipeed-Maixduino-Kit-for-RISC-V-...
I'm not sure what's the status of programming these from Rust. I suppose that you will probably need to build your own toolchain that links the Seeedstudio libraries.
With Rust, you can do what I did with my OS. It can compile out of the box. The kendryte has a "BSP" (base support package) that is essentially a minimal OS, but it is written in C.
It would be unfortunate to have to re-implement the wifi driver in Rust, but I suppose I'll just have to link parts of the C toolchain instead, creating Rust wrappers, etc.
ULP-RISCV has the following features:
support for IMC instruction set
thirty-two 32-bit general-purpose registers
32-bit multiplier and divider
support for interrupts
boot by the CPU, its dedicated timer, or RTC GPIO
https://www.espressif.com/sites/default/files/documentation/...