The premise of the paper is not that branch prediction isn't important for performance, but that it is possible to design an entirely different ISA where it matters much less.

The idea here is to essentially create a branch delay slot instruction, which then can be used to set the latency of a branch such that it doesn't require prediction to not stall the pipeline. Like so:

    dec r1
    basicblock 5  # next five instructions WILL execute, branches after that, if any
    jz exit_loop
    this
    will
    always
    run
    -- branch takes effect here

Then the compiler may commonly reorganize the code such that the variable branch delay instructions perform useful work.