https://newsroom.intel.com/wp-content/uploads/sites/11/2020/...
memory tagging is like a hardware based ASAN that eliminates many memory bugs and improves memory debugging. So its potential is well beyond mitigating ROP (though all these benchmarks will change with memory tagging enabled :-))).
Intel patent document "US2020/0125502 Low memory overhead heap management for memory tagging", has more info on how this might work: https://www.freepatentsonline.com/20200125502.pdf
For a great background primer on why to use this see the brilliant work of Konstantin Serebryany https://arxiv.org/ftp/arxiv/papers/1802/1802.09517.pdf
IMO this is long overdue on Intel architecture and the main reason why one might want to be excited about Tiger Lake
I can imagine it will lead to a lot of effort for Linux: malloc implementation, glibc, compilers, toolchains and debugging tools ... and lots of discussions about why and when it should be enabled. (IMO you want this in production always)