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Comment by brandmeyer | Hacker News Reader

With one notable detail: Its much easier to stream data through the GPU than it is through an FPGA. And I say that fully knowing how much of a (relative) PITA it is to stream data through a GPU.

I think it also works better to think of the DSP resources as a big systolic array with lots of local connectivity and memory and only sparse remote connectivity. The SIMD model doesn't really apply.

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What's annoying is there's no real reason it has to be harder to stream through an FPGA- it's largely just that the ecosystem and FPGA vendor tooling is so utterly garbage that installing it will probably attract raccoons to your /opt.

With one notable detail: Its much easier to stream data through the GPU than it is through an FPGA.

That's an interesting assertion. FPGAs are better at moving data from one place to another than any other general-purpose device I can think of.

How many GPUs have Xilinx GTx-class transceivers, for instance? A GPU with JESD204B/C connectivity would be an extremely interesting piece of hardware.

"Easier" as I'm using it is a metric of engineering effort more than throughput. I don't disagree - there's vastly more aggregate bandwidth available, both internally and on external interfaces.

But its vastly easier to get started with CUDA or OpenCL than it is to get started with a big FPGA.

True, that much certainly isn't debatable.

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