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Comment by samfisher83 | Hacker News Reader

Wow AMD is killing intel in the performance category. I wonder if Intel will have its core2duo chip coming up sometime soon. This is very similar to athlon64 play a decade ago. However with TSMC AMD will have the manufacturing advantage.

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Whlst the TSMC factor has done wonders for AMD now that TSMC overtook Intel. One advantage Intel has still is costs/control of their node and would be very interesting to see production costs compared as might be that Intel has more margin in production they can shave. Though they have stumbled keeping up with node progress and that has clearly been a cornerstone in the hurt they are getting in the market and AMD have capitalised upon that like champs.

Will Intel bring out a new architecture that will rise above all this as they did with the Core2Duo (actually typing this upon one of those cores), well - they need to.

But for me the shift on CPU's does seem to be large and faster cache access and latency. Say Intel released the same chips but added a very large SRAM layer - that for some applications would swing things for sure, not cheap but again - Intel controls and runs their own fabs, and whilst AMD could equally just do that, would the costs in them doing that with TSMC be just as comparable? There is money to be made in fabricating or TSMC would not be doing so well financially of all this. But that is a cost/income that Intel are tapped into with their own fabs.

However it pans, competition has been good for the desktop x86 folks and so glad AMD back in the game and going strong.

One AMD advantage is that it’s manufacturing basically a single part, not the large options of Intel. One part binned and combined into chiplet designs. 8 core to 64 core, its all the same part (1, 2, 4, or 8 of them). There is likely cost savings to this strategy as well.

I imagine they will do that on the GPU side as well at some point.

Also gives them a lot of flexibility with binning which should give them excellent yields.

The ones that don't have full 8 (well enough) working cores just use them for 5600X (6 core) or 5900X (12 cores) if there is 6 or 7 good cores.

The fully working chiplets you can bin for 5800X or 5950X (or for threadripper/Epyc for the very best ones)

Additionally the I/O die on the Ryzen chiplets also gets reused as the X570 chipset, also I believe based on binning.

Bonus: AMD satisfies their contract with Global Foundries by including one I/O die manufactured by GF with every CPU sold.

Intel also uses chip with defected cores for lower core SKUs.

Yes but Intel can't take 2 (or 4 or 8 or whatever number you want) of defective parts and sell it as a high end part. AMD can make a 5900X or a Threadripper/Epyc out of 6 core chiplets "defective". As Intel chips are one big monolithic designs they can't make a 6 core consumer desktop CPU out of a broken 24 or 28 core Xenon chip.

AMD's yields are going to be better too since it's not a monolithic core.

> Say Intel released the same chips but added a very large SRAM layer - that for some applications would swing things for sure, not cheap but again

Which they did for Broadwell but then immediately abandoned it. Anandtech recently did a retrospective on it: https://www.anandtech.com/show/16195/a-broadwell-retrospecti...

(although at the time of writing this Anandtech's site is dead so pop that into your cached lookup of choice)

Intel did perform internal studies on the effect of 3d stacking on CPU layouts. For things like caches the reduction in delay caused by adding another layer is significant. AMD had to increase latency of the L3 cache in Zen 3 by 7 cycles as a trade-off for the increased size. If they were able to stack SRAM with another layer of transistors placed vertically, that latency penalty could be reduced.

That's talking about eDRAM which has different trade-offs due to increased latency vs L3.

Zen4 might bring on-chiplet SRAM cache using a cheaper node

I'm not sure what you're trying to say here. Zen2/3 already have 32MB L3 SRAM on each chiplet. And we know TSMC 5nm is more expensive than 7nm.

I mean on the IO die, not the processor one (or maybe a new one). 256MB L4 Infinity Cache for all the CPUs in the package. It doesn’t need to be on 5nm or 7nm. It can be on 14nm. But still on package.

(I should have said on package, not on-chiplet, too late to edit)

Can you really do an enormous SRAM on a bigger node without it occupying a huge surface? Would 14nm be cheap enough for that to be interesting? If so, why not also use it for other big structures?

IBM does that on mainframes with DRAM as L4. A cluster of four sockets has almost a gigabyte of memory in a separate chip with analogous function as AMD's IO die (and that attaches to the memory modules).

Of course, these are enormous and ridiculously expensive dies.

But eDRAM uses less power than SRAM. A large SRAM on an older process would have a substantial power penalty.

A completely different price-point and TDP, but the Xeon Phi had up to 16GB (out of the main die) that could act as a cache to main memory or mapped to a physical address range. No space for this on this package size, but EPYC package could fit it.

I was pretty sure SRAM uses less power than DRAM. Some research shows it is true for 6T cells, but questionable on smaller 4T cells, depending on implementation.

So, if you can use ~6x the area of eDRAM, you can have almost no power draw SRAM.

Is that just a rumour or are ITK?

Intel could also optimize their high end enthusiast dies by removing iGPUs, since virtually nobody uses or wants them.

And then they could call them kf, and release them last year!

https://ark.intel.com/content/www/us/en/ark/products/190887/...

AFAIK it still has igpu, just non-functional and wasting space

Not as clear-cut on wasting space. Maybe those chips had a defective GPU area and why disabled - would be good to get clarity upon that.

The other aspect is that they will act as a heat spreader at the die level, so whilst not best use of space - given all the factors - not something could easily dismiss and better a waste of space than a waste of a chip who's only crime was to have a non-functioning GPU upon it.

That's not the point. iGPU takes most of the die space. Parents point is it'd be a better end product for enthusiasts had they opt to not put it there in the first place.

Intel's high-end desktop series, the Cascade Lake Xeon W, already lacks graphics.

Intel's out is to actually bring their 7nm node to market. Until then they are a sinking ship and they are certainly well aware of that.

10nm was / is a disaster failure and even if could somehow fenagle it into a usable state by next year will be trounced by tsmc 5nm zen 4. They need to cut their losses and leapfrog or they will stay technologically irrelevant going forward.

Intel does not have a Pentium M design as a backup plan like the last time when the P4 mobile and later desktop efforts reached a dead end.

On mobile they do have the new core architecture, used by ice lake and tiger lake, which at 4ghz were outperforming the previous cores (still used on desktop) at 5ghz.

That we know of, anyway. Jim Keller only just left a few months ago so who knows what’s in the architectural pipeline for the next decade.

You talking about his Intel stint which was cut short for "personal" reasons ???.

Afaik he is not a chip architect anymore - more of organizing engineering teams to perform to their best ability and asking the right questions.

The AMD guy who designed Zen architecture was also responsible for the ill-fated Bulldozer design.

> You talking about his Intel stint which was cut short for "personal" reasons ???.

Those scare quotes are kinda rude, and whatever you're trying to insinuate with them is wrong.

Rude ???.

Clearly a lame PR explanation considering his high profile stature at Intel (he is going to save us) and the suddenness of it all.

https://www.extremetech.com/extreme/311664-intels-jim-keller...

I see they used single quotes .. my bad.

It couldn’t possibly be Jim Keller left on his own accord and that Intel is doing damage control, right? Murthy’s head rolled for picking fights internally, particularly with Raja. Is it such a stretch that Keller wouldn’t want to deal with Intel’s political infighting bullshit and live out his days with family? He’s an accomplished guy and has earned every right to retire or work where he wants to.

You still haven’t explained what was so suspicious about him leaving.

Family, health, there is lots that can happen in life, where work is no longer a priority. Just because it's a common euphemism for something more, doesn't mean it has the be so in this case. Given his great track record, something bad probably happened in his life.

> Given his great track record, something bad probably happened in his life.

I think the implication in the parent comment is that things were so bad at intel that he couldn't fix and chose to leave instead. Whether that's true or not I don't know. But the rumours I've read are not good.

The process matters a whole lot. You can see this with 14nm vs 10nm Intel chips and their power characteristics. The Zen3 core is excellent but if they were forced to use 14nm it would be far less competitive in terms of core count, cache, power, and max clock rate.

When AMD 64 came out it killed the P3 and P4 because of its IO enhancements. By moving the northbridge into the CPU no longer did desktop cpus feel sluggish and no longer would they lock up in IO based tasks. It was a large jump in the desktop space. (Before AMD64 copying a file on your hard drive would run your cpu at 100%. You couldn't multi task and read the news while burning a CD, and so on.)

Intel responded later with the Core 2 Duo, which not only met AMD on its playing field but beat it. For anyone who is wondering how Intel did this, here is an in depth article on the topic: https://www.anandtech.com/print/10525/ten-year-anniversary-o...

The northbridge absolutely would not cause your CPU to lock up on I/O based tasks, and contained an arbiter to balance CPU and I/O initiated memory requests.

The CD burner issues were because they required hard real time control to not screw the disc up.

To add that Core 2 (which was given as an example in the parent post) was still using the traditional north bridge design.

The AMD 64 did not, which is what gave it its large speed boost.

https://www.anandtech.com/show/1098/6

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