I think the HN crowd is mostly excited because it is an ISA that fits two important criteria:
* You can build a RISC-V CPU into your own digital designs for $0. There are also a lot of free designs which use open-source buses like Wishbone if you don't want to build your own.
* Linux/GCC/etc. will probably support a compliant RISC-V implementation.
And the cynical/realist crowd is harrumph-ing after a few important questions, like:
* Many important features are not yet finalized, including things as basic as a nested interrupt controller. So, how compatible will modern RISC-V implementations be with future software?
* Will "good enough" performance actually be good enough? It's still not clear whether a RISC-V CPU will be competitive with ARM et al on power and performance on a similar process node. It might be, but the ecosystem needs to mature.
So it's one of those things that always seems to be 5 years away, like practical fission or the year of the Linux desktop.
But if we ever do get to a point where you can use something like LiteX to generate a RISC-V SoC with N CPUs and driver support for its major peripherals on Linux, that would be exciting. Fabrication on 45-130nm process nodes might also be affordable for small startups by that point, too.