This is a very minor nit, but it's actually a Cortex-M0+ (the plus is significant). Unfortunately the tweet you referenced got that right, so the criticism still stands. See [1] for a short description.

I think I knew that the M0+ lacks the regular load/store exclusive instructions from larger ARMs, handy for implementing synchronization primitives ... odd that they've build a dual core then? No idea how that is supposed to work, but haven't checked the docs either.

Edit: After browsing the (very nice-looking) RP2040 documents, it seems the only atomic thing on the chip is the special "ghosted" I/O access. That will probably be co-opted to implement atomic data structures, but then it will be at the cost of making access to the actual peripheral whose registers are being "stolen" harder or impossible. Strange, hopefully I'm missing something obvious. :)

Also, the PIO peripherals seem awesome! Can't wait to see all the cool things people will pull off with those. The document mentions them being capable of DVI and VGA signalling, even.

[1] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+