Comment by zamadatix | Hacker News Reader

Comment by zamadatix | Hacker News Reader

Parent Full thread

You can give a 5950x all the wattage all day but it really doesn't get much faster until you start dropping the temps to sub ambient. I have a 480mm radiator dedicated to my 5950X along with high quality RAM and extensive tuning (sub timings, fabric clocks) and I'm not able to get anywhere near 6 GHz at room temp without a voltage level that would destroy the chip after a few benchmarks.

And while I think my highly optimized 5950x setup could probably eek out the 12900k cinebench multicore score I'm sure if you gave me 10 minutes to also be fair and tweak a few settings on the 12900K I could get that to win again, even without messing with max power.

I do agree the Ryzen numbers in the article do in general seem lower than normal though.

Given this is Intel's "Catch up multiple nodes, new performance design, 300 watt class, ddr5" CPU and it's only able to get this eek ahead vs AMD's CPU from last year which is about to get the same litany of improvements plus their stacked cache improvement I'm not holding my breath Intel is really innovating fast enough again but at least they don't seem to be sitting still anymore.

What is the cold temp helping with? AFAIK transistors no longer get faster at cold, at least since 16nm the perforamce at sub 1V thin-ox transistors is pretty flat with temperature. Cold helps a lot with power though, leakage at hot (100C) could be 20W, so maybe going cold allowed more dynamic power dissapation? I'd be intersted to hear what the overclock experts like yourself think.

Unless anything has changed the silicon/die itself isn't staying sub ambient at all it's just that there's a limit to hot steep temperature gradient you can build when the ambient/sink temperature is fixed.

Transistors have a maximum operating temperature[1] (Tj_max), and the package has a fixed thermal resistance[2].

If the junction-to-case thermal resistance is 0.5 deg C/W and CPU dissipates 100W, then the junction will operate at 50 deg C above the case temperature, whatever that is.

If the case is kept at room temperature (say 25 deg C), which is the best possible a simple air or water cooled system can do, then the junction will operate at 75 deg C.

For simple discrete transistors and diodes, Tj_max is typically 150-175 deg C. For modern CPUs I believe it's closer to 100-125 deg C.

Thus, lowering the case temperature means the chip can consume more power before reaching the maximum junction temperature.

A greater power budget means you could raise operating voltages to help with overclocking for example. Keep in mind power dissipation scales with voltage squared.

There might be other effects too, I'm no overclocking expert, but this is one aspect.

[1]: https://en.wikipedia.org/wiki/Junction_temperature

[2]: https://en.wikipedia.org/wiki/Thermal_resistance

Leakage increases with temperature, and the speed at which FET switches also increases with temperature.

Speed, is that due to Vgs threshold voltage decreasing as temp increases? On the other hand you have Rds(on) rising as temp increases, which would negate some of that effect I would imagine (lower gate drive current).

But not my field so no idea how that interplay works out.

Carrier injection speed is a function of temperature.

Think of FET as a solid state thermionic valve, it's not that far away from it, if you dig into physics.

Thanks. You definitely don't want the junction temp anywhere near 125c, the leakage would be very high. I thought most processors in due temp was 75-85c max, and will throttle severely if it goes above that.

Tj_max is listed under "absolute maximum ratings", so indeed operating conditions should be well below that. I see I was a bit sloppy in my wording.

The cold temperature increases the clocks that AMD's boosting algorithm will request. See here for a demonstration using LN2: https://www.youtube.com/watch?v=g94rNe4XSGU

If 5950x was designed for 240W max power like 12900k, then it is likely that the optimizations AMD would have needed to implement in the silicon would have also provided some additional frequency headroom. It's all hypothetical though since all we can do is compare the chips that were actually produced.

Reply on news.ycombinator.com