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Comment by kens | Hacker News Reader

Author here if anyone has questions about the chip...

The block-diagram level breakdown of the different sections of silicon is really a wonderfully helpful way to look at this. It makes the zoomed in view of each section more meaningful. Then seeing the die photo of individual transistors or groups of them, next to schematic level interpretation, really drives it home. Thanks for making something so instructive.

Have you decapped other sound-making devices? The greeting card chip makes me think of the ubiquitous "laser noise" chip from countless 80's kids toys. That or one of the many kid's keyboards or baby noise console devices, that have all of the function inside a single epoxy-blobbed die. It would be pretty fascinating to see a similar breakdown of which sections encode samples, note values, rhythm and sequences, control inputs, etc.

Your description immediately made me think of the TI SN76577 "Complex Sound Generator" IC [1]. If I'm not mistaken it was used in the early versions of the MB Games Electronic Battleship game (think falling missile and white-noise explosion sounds).

Edit: Not a decap, but this page [2] has links to the datasheet and other reference material that includes a block diagram, and even has circuit diagrams of the internal circuitry.

Edit 2: A video [3] demonstrating some of the possible sounds.

[1] https://en.wikipedia.org/wiki/Texas_Instruments_SN76477 [2] http://sandsoftwaresound.net/sn76477-complex-sound-generator... [3] https://www.youtube.com/watch?v=atH1MvXDYYE

Coincidentally, I've written about that chip :-) http://www.righto.com/2017/04/reverse-engineering-76477-spac...

Nice!

One of my earliest memories is my grandmother giving me a musical christmas card that played a medley of Jingle Bells and Santa Claus is Coming to Town. I thought it was the cutest thing ever. This had to have been it. Thank you so much for reminding me of this old memory on Christmas. :)

I’ve been following your blog for a while and just wanted to thank you for your work. Keep it up! :)

Is it possible that your "Structure of an inverter" image is mislabed? NMOS would be on the left and PMOS on the right. My thinking is the PMOS has the extra diffusion step to create the n-well for the channel under the gate.

It's quite possible that they are reversed; I'm sort of guessing. PMOS transistors are usually bigger, so I think it's the one on the left. The chip could have n-wells or p-wells, so it could go either way with the extra diffusion.

Can boiling sulfuric acid like you used to dissolve the epoxy package be used to successfully de-bayer a CMOS camera sensor?

You'd think someone would have a service dedicated to this, but I've wanted a monochrome dslr or mirrorless for like a decade and a half, already.

Preferably Nikon, but my limited understanding is that the canon sensors are easier to debayer.

Crazy thing is you can buy the same sensors monochrome for industrial and astro applications but the cameras are twice as expensive.

Eg Sony IMX455 61MP sensor in the $4k ASI6200: https://astronomy-imaging-camera.com/product/asi6200mm-pro-m...

The cheapest I have seen an IMX455 in a new camera is $3000 for the Sony A7RIV when it’s on sale. And that doesn’t have a lens. Once one has a couple of lenses, a case, a tripod, filters, and memory cards, we’re in the $5000 ballpark.

The IMX455 is an incredible hi end sensor; there’s only about three medium format sensors that exist with higher resolution—forget getting one of those for “only” $5000—but the cost of entry to have one in a usable camera is pretty substantial.

Maybe; I haven't tried that. I don't know what the Bayer layer is made of; if it's glass, you'd need HF or something nasty.

What is the "options" section in the block diagram? Does that represent the debug functionality you mention on unexposed pins? Anything else interesting that someone could do with these chips in a different package?

> The chip has 3 pins, but there are 8 pads on the die. The other pins appear to be used for testing. By activating one of the pins, the chip can be put into a test mode. The test mode runs through the songs at 512× speed so the chip can be tested quickly without waiting for the tunes to play. The other test pins appear to expose other internal data for testing.

This makes me wonder if you put one of the other test pins on a scope, if you'd see a pattern representing the song or sequence, allowing quick verification of the chip. I think at 512x speed, even a more limited storage scope of the era of these chips could capture the full output on-screen. Each flavor of the chip probably had an expected pattern based on ROM which could be checked.

I'm imagining a technician sitting at a test bench, having to do verification work on these all day, thankful for having a test pin instead of having to listen to the same dang beeping song over and over :)

The options are things such as staccato notes vs held notes or making the chip loop continuously. These are implemented in the logic section through connections in the metal layer to power or ground. In other words, different versions of the chip have the metal layer constructed slightly differently to obtain different behavior.

Nice work!

How many transistors does it have in all?

They could have used an LFSR for the PC too. Would that have saved some area? If not, I wonder why they used them elsewhere.

Are the resets (on 10000...) synchronous? If not I wonder how they handled glitch safety.

I estimate about 1500 transistors. Yes, they could have used the LFSR for the PC; I've seen that in early microcontrollers. I actually expected to see a LFSR there. Maybe they wanted to have a linear ROM layout to make their life simpler.

Yes, the resets are synchronous.

Thank you very much!

I wonder if you could do a CMOS μC in 1500 transistors; my best ideas so far are barely under 3000. Of course to make music that way you need a much faster clock plus some code memory.

The Intel 4004 had 2250 transistors, and it was designed to work in concert with support chips, unlike a modern MCU. A quick search doesn't turn up any known models with fewer. 1500 for an MCU might be possible, but it'd be a tight squeeze. Registers and multiplexers chew through transistors rather quickly.

The 4004 had to go fast enough to run a calculator at 0.75 MHz though. A modern chip typically runs at 100 MHz and can run at 4 GHz. If you could fab it in indium phosphide (which wouldn't be CMOS!) you could maybe run it at 400 GHz and use an optical fiber as a delay-line memory, 1 bit per millimeter. This sort of thing might enable you to use less transistors than a 4004.

I got down about that low with a bit-serial design whose only arithmetic instruction was a subtract, but I haven't simulated it at even the RTL level, just done a gate-level design on paper and a couple of software instruction-level sims.

Can you post a video of all songs?

My parents had that card when I was a kid, it really was great.

Excellent work Ken, as always. Love the detail.

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