Early systems with TSC and multiple processors (or possibly multiple cores) either didn't synchronize the TSCs or may have done a poor job. If you've got a cpu that reports constant TSC, the rate is declared to not change when the cpu clock is modulated, but it may pause in some low power states. If the cpu reports invariant TSC, it should continue running in all cpu states other than power off.
Anything new enough to have invariant tsc probably has at least all the cores in a single socket properly synchronized. Multi-socket you'd need to read docs or kernel code to know what's specified. OSes often prefer tsc timekeeping, if available, so they've got rules by hardware generation and tests to run when it's not clear. There's some cases where the OS attempts to synchronize the TSCs as well (such as CPU hotplug or startup firmware didn't sync), but they only stay in sync if the clock source for the counter is the same or at least linked.
Hope this helps you find more info.